FPGA开发中verilog语言一个小问题求解

module ShitReg(cp, rst, din, dout);

input cp;
input rst;
input din;
output reg [7:0] dout;

reg regin;

key_clk FF0(cp, din, regin);

always @(posedge cp or posedge rst)
begin
if(rst)
dout = 8'b11111111;
//else begin
dout = dout << 1;
dout[0] = regin;
//end
end

endmodule

module key_clk(clk, in, out); //去抖动
input clk;
input in;
output reg out;
reg in1;
reg in2;
reg count; //计数器宽度？？？

always @( posedge clk)//CLK 50M
begin
count <= count+1;
if(count == 500000)
begin
in1 <= in;
count <= 0;
end
in2 <= in1;
out <= in2 & (!in1);
end
endmodule

代码写的很不规范，问题较多～